During the ISCAS 2026 conference, Tingbo He, the president of Huawei Semiconductor, officially unveiled the technical specifications for the upcoming Kirin chip line and a roadmap extending to 2031. The autumn flagship processor, currently known as Kirin 2026, marks the first application of LogicFolding technology. This method employs a three dimensional logical fold of the crystal rather than the traditional two dimensional architecture.
Relative to standard 2D architecture, the new method delivers a transistor density of 238 MTr/mm², which is a 53.5 per cent increase. Energy efficiency for P cores improves by 41 per cent, and peak frequency has risen 12.7 per cent to approximately 3.1 GHz. Huawei refers to this transition as a shift towards a fully foldable direction for the next decade.
Presentation slides indicate yearly growth in specifications. Frequency targets are set at 3.71 GHz for 2028 and 4.3 GHz for 2030. By 2031, Huawei predicts density will double to over 400 MTr/mm² with a frequency near 5.0 GHz. Development continues on the Atlas AI accelerator line as well. The Atlas960 model is planned for 2027 and should achieve 60 EFLOPS, whereas Atlas950 delivers 8 EFLOPS this year.
Digital Chat Station suggests that the inaugural chip utilising LogicFolding, Kirin 2026, will launch as part of the Huawei Mate 90 series. Nevertheless, Huawei has not provided any confirmation on the matter.
Source: Digital Chat Station and Huawei
